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HSP48410
Data Sheet July 2004 FN3185.3
Histogrammer/Accumulating Buffer
The Intersil HSP48410 is an 84 lead Histogrammer IC intended for use in image and signal analysis. The on-board memory is configured as 1024 x 24 array. This translates to a pixel resolution of 10 bits and an image size of 4k x 4k with no possibility of overflow. In addition to Histogramming, the HSP48410 can generate and store the Cumulative Distribution Function for use in Histogram Equalization applications. Other capabilities of the HSP48410 include: Bin Accumulation, Look Up Table, 24-bit Delay Memory, and Delay and Subtract mode. A Flash Clear pin is available in all modes of operation and performs a single cycle reset on all locations of the internal memory array and all internal data paths. The HSP48410 includes a fully asynchronous interface which provides a means for communications with a host, such as a microprocessor. The interface includes dedicated Read/Write pins and an address port which are asynchronous to the system clock. This allows random access of the Histogram Memory Array for analysis or conditioning of the stored data.
Features
* 10-Bit Pixel Data * 4k x 4k Frame Sizes * Asynchronous Flash Clear Pin * Single Cycle Memory Clear * Fully Asynchronous 16 or 24-Bit Host Interface * Generates and Stores Cumulative Distribution Function * Look Up Table Mode * 1024 x 24-Bit Delay Memory * 24-Bit Three State I/O Bus * DC to 40MHz Clock Rate
Applications
* Histogramming * Histogram Equalization * Image and Signal Analysis * Image Enhancement * RGB Video Delay Line
Ordering Information
PART NUMBER HSP48410JC-33 TEMP. RANGE (C) 0 to 70 PACKAGE 84 Ld PLCC PKG. DWG. # N84.1.15
Block Diagram
24 24
HISTOGRAM MEMORY ARRAY MUX 24 DATA IN DATA OUT 24 ADDER DIO0-23 DIO INTERACE
DIN0-23
PIN0-9
10 ADDRESS GENERATOR
10
ADDRESS
IOADD0-9
10
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright Harris Corporation 1999, Copyright Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HSP48410 Pinouts
84 LEAD PLCC
GND PIN9 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 PIN6 PIN7 PIN8 VCC DIN6 DIN7 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 GND DIO8 DIO9 DIO10 DIO11 DIO12 DIO13 DIO14 DIO15 DIO16 DIO17 DIO18 DIO19 PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 CLK
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 FC RD START LD FCT2 FCT1 FCT0 WR GND UWS IOADD9 IOADD8 IOADD7 IOADD6 IOADD5 IOADD4 IOADD3 IOADD2 IOADD1 IOADD0 VCC 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DIN8 DIN9 DIN10 DIN11 DIN12 DIN13 DIN14 DIN15 DIN16 DIN17 GND DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 DIO23 DIO22 DIO21 DIO20
Pin Description
NAME CLK PLCC PIN 1 TYPE I DESCRIPTION Clock Input. This input has no effect on the chips functionality when the chip is programmed to an asynchronous mode. All signals denoted as synchronous have their timing specified with reference to this signal. Pixel Input. This input bus is sampled by the rising edge of clock. It provides the on-chip RAM with address values in Histogram, Bin Accumulate and LUT(write) mode. During Asynchronous modes it is unused. The Load pin is used to load the FCT0-2 bits into the FCT Registers. (See below). These three pins are decoded to determine the mode of operation for the chip. The signals are sampled by the rising edge of LD and take effect after the rising edge of LD. Since the loading of this function is asynchronous to CLK, it is necessary to disable the START pin during loading and enable START at least 1 CLK cycle following the LD pulse. This pin informs the on-chip circuitry which clock cycle will start and/or stop the current mode of operation. Thus, the modes are asynchronously selected (via LD) but are synchronously started and stopped. This input is sampled by the rising edge of CLK. The actual function of this input depends on the mode that is selected. START must always be held high (disabled) when changing modes. This will provide a smooth transition from one mode to the next by allowing the part to reconfigure itself before a new mode begins. When START is high, LUT(read) mode is enabled except for Delay and Delay and Subtract modes. Flash Clear. This input provides a fully asynchronous signal which effectively resets all bits in the RAM Array and the input and output data paths to zero.
PIN0-9
3-11, 83
I
LD FCT0-2
15 16-18
I I
START
14
I
FC
12
I
2
HSP48410 Pin Description
NAME DIN0-23 DIO0-23 PLCC PIN 58-63, 65-82 33-40, 42-57 22-31 21 TYPE I I/O DESCRIPTION Data Input Bus. Provides data to the Histogrammer during Bin Accumulate, LUT, Delay and Delay and Subtract modes. Synchronous to CLK. Asynchronous Data Bus. Provides RAM access for a microprocessor in preconditioning the memory array and reading the results of the previous operation. Configurable as either a 24 or 16-bit bus. RAM address in asynchronous modes. Sampled on the falling edge of WR or RD. Upper Word Select. In 16-bit Asynchronous mode, a one on this pin denotes the contents of DIO0-7 as being the upper eight bits of the data in or out of the Histogrammer. A zero means that DIO0-15 are the lower 16 bits. In all other modes, this pin has no effect. Write enable to the RAM for the data on DIO0-23 when the HSP48410 is configured in one of the asynchronous modes. Asynchronous to CLK. Read control for the data on DIO0-23 in asynchronous modes. Output enable for DIO0-23 in other modes. Asynchronous to CLK. +5V. 0.1F capacitors between the VCC and GND pins are recommended. Ground
IOADD0-9 UWS
I I
WR RD VCC GND NOTES:
19 13 2, 32 20, 41, 64, 84
I I
1. An overbar denotes an active low signal. 2. Bit 0 is the LSB on all buses.
Functional Description
The Histogrammer is intended for use in signal and image processing applications. The on-board RAM is 24 bits by 1024 locations. For histogramming, this translates to an image size of 4k x 4k with 10-bit data. A Functional Block Diagram of the part is shown in Figure 1. In addition to histogramming, the HSP48410 will also perform Histogram Accumulation while feeding the results back into the memory array. The on-board RAM will then contain the Cumulative Distribution Function and can be used for further operation such as histogram equalization. Other modes are: Bin Accumulate, Look Up Table (LUT), Delay Memory, and Delay and Subtract. The part can also be accessed as a 24-bit by 1024 word asynchronous RAM for preconditioning or reading the results of the histogram. The Histogrammer can be accessed both synchronously and asynchronously to the system clock (CLK). It was designed to be configured asynchronously by a microprocessor, then switched to a synchronous mode to process data. The result of the processing can then be read out synchronously, or the part can be switched to one of the asynchronous modes so the data may be read out by a microprocessor. All modes are synchronous except for the Asynchronous 16 and 24 modes. A Flash Clear operation allows the user to reset the entire RAM array and all input and output data paths in a single cycle.
Histogram Memory Array
The Histogram Memory Array is a 24-bit by 1024 deep RAM. Depending on the current mode, its input data comes from either the synchronous input DIN0-23, from the asynchronous data bus DIO0-23, or from the output of the adder. The output data goes to the DIO bus in both synchronous and asynchronous modes.
Address Generator
This section of the circuit determines the source of the RAM address. In the synchronous modes, the address is taken from either the output of the counter or PIN0-9. The pixel input bus is used for Histogram, Bin Accumulate, and LUT(read) modes. All other synchronous modes, i.e. Histogram Accumulate, LUT(write), Delay, and Delay and Subtract use the counter output. The counter is reset on the first rising edge of CLK after a falling edge on START. During asynchronous modes, the read and write addresses to the RAM are taken from the IOADD bus on the falling edge of the RD and WR signals, respectively.
Adder Input
The Adder Input Control Section contains muxes, registers and other logic that provide the proper data to the adder. The configuration of this section is controlled by the output of the Function Decode Section.
3
HSP48410
DIO Interface
The DIO Interface Section transfers data between the Histogrammer and the outside world. In the synchronous modes, DIO acts as a synchronous output for the data currently being processed by the chip; RD acts as the output enable for the DIO bus; WR and IOADD0-9 have no effect. When either of the Asynchronous modes are selected (16 or 24-bit), the RAM output is passed directly to the DIO bus on read cycles, and on write cycles, data input on DIO goes to the RAM input port. In this case, data reads and writes are controlled by RD, WR and IOADD0-9.
FCT 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 Histogram Histogram Accumulate Delay and Subtract Look Up Table Bin Accumulate Delay Memory Asynchronous 24 Asynchronous 16 MODE TABLE 1. FUNCTION DECODE
Function Decode
This section provides the signals needed to configure the part for the different modes. The eight modes are decoded from FCT0-2 on the rising edge of LD (see Table 1). The output of this section is a set of signals which control the path of data through the part. The mode should only be changed while START is high. After changing from one mode to another, START must be clocked high by the rising edge of CLK at least once.
Flash Clear
Flash Clear allows the user to clear the entire RAM with a single pin. When the FC pin is low, all bits of the RAM and the data path from the RAM to DIO0-23 are set to zero. The FC pin is asynchronous with respect to CLK: the reset begins immediately following a low on this signal. For synchronous modes, in order to ensure consistent results, FC should only be active while START is high. For asynchronous modes, WR must remain inactive while FC is low.
Functional Block Diagram
DIO I/F DIO 0-23
DIN 0-23 REG REG REG
MUX
24X1024 RAM IN OUT ADDRESS ADDER INPUT CONTROL
MUX REG
IOADD 0-9 PIN 0-9 REG
ADDRESS GENERATOR
CLK WR RD UWS START FC CONTROL
COUNTER
TO ADDRESS GENERATOR TO OUTPUT STAGE TO RAM
FCT 0-2 LD
FUNCTION DECODE
MUX CONTROL SIGNALS
ALL REGISTERS ARE CLOCKED BY CLK
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
4
HSP48410 Histogram Mode
This is the fundamental operation for which this chip was intended. When this mode is selected, the chip configures itself as shown in the Block Diagram of Figure 2. The pixel data is sampled on the rising edge of clock and used as the read address to the RAM array. The data contained in that address (or bin) is then incremented by 1 and written back into the RAM at the same address. When the operation is complete, the RAM will contain the Cumulative Distribution Function (CDF) of the image. Figure 4 shows the configuration for this mode. Once this function is selected, the START pin is used to reset the counter and enable writing to the RAM. Write enable is delayed 3 cycles to match the delay in the Address Generator. The START pin determines when the accumulation will begin. Before this pin is activated, the counter will be in an unknown state and the DIO bus will contain unpredictable data. Once the START pin is sampled low, the data registers are reset in order to clear the accumulation. The output (DIO bus) will then be zero until a nonzero data value is read from the RAM. Timing for this operation is shown in Figure 5.
IN
S "0" MUX PIN 0-9 ADDRESS GENERATOR
REG
RAM OUT WR ADDRESS
REG
DIO DIO 0-23 I/F
RD IN OUT REG RAM
REG
"1"
ADDRESS START S CONTROL ADDRESS GENERATOR REG
DIO DIO 0-23 I/F
RD
FIGURE 2. HISTOGRAM MODE BLOCK DIAGRAM
At the same time, the new value is also displayed on the DIO bus. This procedure continues until the circuit is interrupted by START returning high. When START is high, the RAM write is disabled, the read address is taken from the Pixel Input bus, and the chip acts as if it is in LUT(read) mode. Figure 3 shows histogram mode timing. START is used to disregard the data on PIN0-9 at DATA2. START is sampled on the rising edge of clock, but is delayed internally by 3 cycles to match the latency of the Address Generator. Data is clocked onto the DIO bus on the rising edge of CLK. RD acts as output enable.
CLK
COUNTER
START
CONTROL
FIGURE 4. HISTOGRAM ACCUMULATE MODE BLOCK DIAGRAM
CLK CLK START PIN 0-9 DIO 0-23 (RD LOW) DATA 0 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 START DIO 0-23 (RD LOW)
OUT 0 OUT 1 OUT 2
OUT 0 OUT 1 OUT 2 ORIGINAL BIN CONTENTS ARE NOT UPDATED
FIGURE 5. HISTOGRAM ACCUMULATE MODE TIMING
FIGURE 3. HISTOGRAM MODE TIMING
Histogram Accumulate Mode
This function is very similar to the Histogram function. In this case, a counter is used to provide the address data to the RAM. The RAM is sequentially accessed, and the data from each bin is added to the data from the previous bins. This accumulation of data continues until the function is halted. The results of the accumulation are displayed on the DIO bus while simultaneously being written back to the RAM.
The START pin must remain low in order to allow the accumulated data to overwrite the original histogram data contained in the RAM. When the START pin returns to a high state, the configuration remains intact, but writing to the RAM is disabled and the part is in LUT(read) mode. Note that the counter is not reset at this point. The counter will be reset on the first cycle of CLK that START is detected low. To prevent invalid data from being written to the RAM, when the counter reaches its maximum value (1023), further writing to the RAM is disabled and the counter remains at this value until the mode is changed.
5
HSP48410
At the end of the histogram accumulation, the DIO output bus will contain the last accumulated value. The chip will remain in this state until START becomes inactive. The results of the accumulation can then be read out synchronously by keeping START high, or asynchronously in either of the asynchronous modes. The transformation function can be loaded into the LUT in one of three ways: in LUT mode, through DIN0-23; in either asynchronous mode, over the DIO bus as described below under Asynchronous 16/24 Modes; in the Histogram Accumulate mode the transformation function is calculated internally (see description above). The transformation function can then be utilized by deactivating START, putting the part in LUT mode and clocking the data to be transformed onto the PIN bus. Note that it is necessary to wait one clock cycle after changing the mode before clocking data into the part. The Block Diagram and Timing Diagram for this mode are shown in Figures 8 and 9. The left half of the timing diagram shows LUT(write) mode. On the first CLK that detects START low, the counter is reset and the write enable is activated for the RAM. As long as START remains low, the counter provides the write address to the RAM and data is sequentially loaded through the DIN bus. The DIN bus is delayed internally by 3 cycles to match the latency in the Address Generator. The DIO bus will contain the previous contents of the memory location being updated. When 1024 words have been written to the RAM, the counter stops and further writes to the RAM are disabled. The part stays in this state while START remains low. When START returns high, the RAM write is disabled, the read address is taken from the PIN bus, and the chip acts as a synchronous LUT. (This is known as LUT(read) mode.) In order to ensure that the internal pipelines are clear, data should not be input to PIN0-9 until the third clock after START goes high.
Bin Accumulate Mode
The functionality of this mode is also similar to the Histogram function. The only difference is that instead of incrementing the bin data by 1, the bin data is added to the incoming DIN bus data. The DIN bus is delayed internally by 3 cycles to match the latency in the address generator. Figure 6 shows the block diagram of the internal configuration for this mode, while the timing is given in Figure 7. Note that in this figure, START is used to disregard the data on DIN0-23 during DATA2.
RAM IN OUT REG
ADDRESS REG REG REG DIN 0-23 REG MUX DIO DIO 0-23 I/F
"0" REG PIN 0-9 ADDRESS GENERATOR RD
START
CONTROL
FIGURE 6. BIN ACCUMULATE BLOCK DIAGRAM
REG REG REG IN OUT REG DIN 0-23 RAM
CLK START REG ADDRESS PIN 0-9 ADD. 0 DATA DIN 0-23 DIO 0-23 (RD LOW) DATA 0 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 OUTPUT OUT 0 OUT 1 OUT 2 START CLK COUNTER ADD. 1 ADD. 2 ADD. 3 ADD. 4 ADD. 5 PIN 0-9 ADDRESS GENERATOR "0"
REG
WR ADDRESS
DIO DIO 0-23 I/F
RD
ORIGINAL BIN CONTENTS ARE NOT UPDATED
CONTROL
FIGURE 7. BIN ACCUMULATE TIMING
Look Up Table Mode
A Look Up Table (LUT) is used to perform a fixed transformation function on pixel values. This is particularly useful when the transformation is nonlinear and cannot be realized directly with hardware. An example is the remapping of the original pixel values to a new set of values based on the CDF obtained through Histogram Accumulation. 6
FIGURE 8. LOOK UP TABLE BLOCK DIAGRAM
HSP48410 Delay and Subtract Mode
CLK START DATA DIN 0-23 0 1 2 3 4 5 ADDRESS REG REG REG 0 OUTPUT DIO 0-23 0* 1* 2* 3* 0 1 2 3 IN OUT REG PIN 0-9 DIN 0-23 RAM (WRITE) (READ)
This mode is similar to the Delay Memory mode, except the input data is subtracted from the corresponding data stored in RAM (See Figures 12 and 13).
* PREVIOUS CONTENTS OF BIN LOCATION.
FIGURE 9. LOOK UP TABLE MODE TIMING
CLK
TWO'S COMPLEMENT RD
COUNTER
Delay Memory (Row Buffer) Mode
As seen by comparing Figures 8 and 10, the configuration for this mode is nearly identical to the LUT mode. In this mode, however, the counter is always providing the address and the write function is always enabled. In order to force this configuration to act as a row delay register, the START signal must be used to reset the internal counter each time a new row of pixels is being sampled. Because of the inherent latency in the address and data paths, the counter must be reset every N-4 cycles, where N is the desired delay length. For example, if a delay from DIN to DIO of ten cycles is desired, the START signal must be set low every six cycles (see Figure 11). If the internal address counter reaches its maximum count (1023), it holds that value and further writes to the RAM are disabled.
START CONTROL
FIGURE 12. DELAY AND SUBTRACT BLOCK DIAGRAM
CLK
START DATA DIN 0-23 1 OUTPUT DIO 0-23 DATA 1 MINUS DATA 7 2 3 4 5 6 7 8 9 10 11 12 13 14
MODIFIED DATA 1 2 3 4 5
REG
ADDRESS
DIO DIO 0-23 I/F
REG
REG
REG
IN
OUT
REG
DIN 0-23
RAM
DATA 2 MINUS DATA 8
CLK
COUNTER
"0" RD
REG
ADDRESS
DIO DIO 0-23 I/F
FIGURE 13. DELAY AND SUBTRACT MODE TIMING FOR ROW LENGTH OF TEN
Asynchronous 16/24 Modes
In the Asynchronous modes, the chip acts like a single port RAM. In this mode, the user can read (access) any bin location on the fly by simply setting the 10-bit IO address to the desired bin location. The RAM is then read or written on the following RD or WR pulse. A block diagram for this mode is shown in Figure 14. Note that all registers and pipeline stages are bypassed; START and CLK have no effect in this mode. Timing waveforms for this mode are also shown in Figure 15. During reading, the read address is latched (internally) on the falling edge of RD. During write operations, the address is latched on the falling edge of WR and data is latched on the rising edge of WR. Note that reading and writing occur on different ports, so that, in this mode, the write port always latches its address and data values from the WR signal, while the read port always uses RD for latching.
START
CONTROL
FIGURE 10. DELAY MEMORY BLOCK DIAGRAM
CLK START DATA DIN 0-23 1 2 3 4 5 6 7 8 9 10 11 12 13 14
DIO 0-23
1
2
3
4
5
FIGURE 11. DELAY MEMORY MODE TIMING FOR ROW LENGTH OF TEN
7
HSP48410
The difference between the Async 16 mode and the Async 24 mode is the number of data bits available to the user. In 16-bit mode, the user can connect the system data bus to the lower 16 bits of the Histogrammer's DIO bus. The UWS pin becomes the LSB of the IO address, which determines if the lower 16 bits or upper 8 bits of the 24-bit Histogrammer data is being used. When UWS is low, the data present at DIO0-15 is the lower 16 bits of the data in the IOADD0-9 location. When UWS is high, the upper 8 bits of the IOADD09 location are present on DIO0-7. (This is true for both reading and writing). Thus, it takes 2 cycles for an asynchronous 24-bit operation when in Async 16 mode. Unused outputs are zeros.
WRITE CYCLE TIMING WR RD IOADD 0-9, UWS DIO 0-23
READ CYCLE TIMING WR RD IOADD 0-9, UWS
DIO I/F 24x1024 RAM IN OUT WR ADDRESS
DIO 0-23
DIO 0-23
FIGURE 15. ASYNCHRONOUS 16/24 MODE TIMING
IOADD 0-9
ADDRESS GENERATOR
WR RD UWS
CONTROL
FIGURE 14. ASYNCHRONOUS 16/24 BLOCK DIAGRAM
8
HSP48410
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V Input, Output Voltage . . . . . . . . . . . . . . . . . . GND-0.5V to VCC+0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Maximum Storage Temperature Range . . . . . . . . . . -65C to 150C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (PLCC - Lead Tips Only)
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3500 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER Logical One Input Voltage Logical Zero Input Voltage High Level Clock Input Low Level Clock Input Output High Voltage Output Low Voltage Input Leakage Current I/O Leakage Current Standby Supply Current Operating Power Supply Current NOTES: 4. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 12mA/MHz. 5. Maximum junction temperature must be considered when operating part at high clock frequencies. SYMBOL VIH VIL VIHC VILC VOH VOL IL IO ICCSB ICCOP MIN 2.0 3.0 2.6 -10 -10 DMAX 0.8 0.8 0.4 10 10 500 396 UNITS V V V V V V A A A mA TEST CONDITIONS VCC = 5.25V VCC = 4.75V VCC = 5.25V VCC = 4.75V IOH = -400A, VCC = 4.75V IOL = +2.0mA, VCC = 4.75V VIN = VCC or GND, VCC = 5.25V VOUT = VCC or GND, VCC = 5.25V VIN = VCC or GND, VCC = 5.25V, Outputs Open f = 33 MHz, VIN = VCC or GND VCC = 5.25V (Notes 4, 5)
Capacitance TA = 25C, Not tested, but characterized at initial design and at major process or design changes.
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN MAX 12 12 UNITS pF pF TEST CONDITIONS FREQ = 1 MHz, VCC = Open, all measurements are referenced to device ground.
AC Electrical Specifications
PARAMETER Clock Period Clock Low Clock High DIN Setup DIN0-23 Hold Clock to DIO0-23 Valid FC Pulse Width FCT0-2 Setup to LD
VCC = 5V 5%, TA = 0C to 70C (Note 6) -40 (40 MHz) SYMBOL tCP tCH tCL tDS tDH tDO tFL tFS NOTES MIN 25 10 10 12 0 35 10 MAX 15 -33 (33 MHz) MIN 30 12 12 13 0 35 10 MAX 19 UNITS ns ns ns ns ns ns ns ns
9
HSP48410
AC Electrical Specifications
PARAMETER FCT0-2 Hold from LD START Setup to CLK START Hold from CLK PIN0-9 Setup Time PIN0-9 Hold Time LD Pulse Width LD Setup to START WR Low WR High Address Setup Address Hold DIO Setup to WR DIO Hold from WR RD Low RD High RD Low to DIO Valid Read/Write Cycle Time DIO Valid after RD High Output Enable Time Output Disable Time Output Rise Time Output Fall Time NOTES: 6. AC Testing is performed as follows: Input levels (CLK) 0.0V and 4.0V; input levels (all other inputs) 0V and 3.0V. Timing reference levels (CLK) = 2.0V, (all others) = 1.5V. Output load circuit with CL = 40pF. Output transition measured at VOHS 1.5V and VOL 1.5V. 7. There must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START. 8. Characterized upon initial design and after major changes to design and/or process. 9. Transition is measured at 200mV from steady state voltage with loading as specified in test load circuit with CL = 40pF. VCC = 5V 5%, TA = 0C to 70C (Note 6) (Continued) -40 (40 MHz) SYMBOL tFH tSS tSH tPS tPH tLL tLS tWL tWH tAS tAH tWS tWH tRL tRH tRD tCY tOH tOE tOD tR tF Note 8 Note 9 Note 8 From 0.8V to 2.0V, Note 8 From 2.0V to 0.8V, Note 8 Note 7 NOTES MIN 0 12 0 12 0 10 TCP 12 12 13 1 12 1 35 15 55 35 0 18 18 6 6 MAX -33 (33 MHz) MIN 0 13 0 13 0 12 TCP 15 15 15 1 15 1 43 17 65 MAX 43 0 19 19 6 6 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Test Load Circuit
DUT CL
S1
INCLUDES STRAY AND JIG CAPACITANCE
SWITCH S1 OPEN FOR ICCSB AND ICCOP
IOH
1.5V
IOL
EQUIVALENT CIRCUIT
10
HSP48410
i
Waveforms
tCH CLK tDS DIN0-23 tPS PIN0-9 START tDO DIO0-23 SYNCHRONOUS OUTPUT TIMING tSS tSH START tSH tSS DIO0-23 RD tOE tOD tPH CLK tLS t DH t CP tLL tCL LD tFS FCT0-2
tFH
FIGURE 16. SYNCHRONOUS DATA AND CONTROL TIMING
FIGURE 17. FUNCTION LOAD TIMING
tWL WR RD IOADD0-9 tWDS DIO0-23 tAS tAH
tWH
WR tRL RD tAS IOADD0-9 tRD tOD tAH tRH
tWDH
DIO0-23
FIGURE 18. WRITE CYCLE TIMING
FIGURE 19. READ CYCLE TIMING
tFL FC 2.0 V 0.8 V
tR
tF
FIGURE 20. FLASH CLEAR TIMING
FIGURE 21. OUTPUT RISE AND FALL TIMES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11

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